The present invention generally relates to fabricating nonvolatile semiconductor memory devices. In particular, the present invention relates to improved methods of fabricating flash memory devices with bit lines that can serve as sources and/or drains.
A desire for compact size and high access speed has driven the development of EEPROM (electrically erasable programmable read only memory) flash memory devices. One such development, applicable to both conventional and SONOS (silicon-oxide-nitride-oxide-silicon) flash memory devices, provides a virtual ground array structure. While a non-virtual ground array structure has dedicated source and drain regions for reading and writing operations, a virtual ground array structure reduces the spacing between gates by employing bit lines that can serve as either sources or drains according to the voltages applied.
Reducing the size of flash memory devices increases their speed, but speed can be enhanced in other ways. In a large array, speed is enhanced by reducing the spacing between contacts along bit lines. Contacts take up room and generally require a broader spacing between adjacent word lines wherever the contacts are to be placed. A compromise between the gains of more narrowly spaced contacts and the cost of having more contacts is to place contacts along the bit lines at every 16 word lines.
The response delay associated with polysilicon word lines can be reduced by siliciding, which provides lower electrical resistance. Siliciding is generally carried out without masking in what is referred to as a self-aligned siliciding process (saliciding). Unfortunately, saliciding has proven difficult in virtual ground arrays. The saliciding process has a tendency to cause shorting between bit lines, particularly in the absence of oxide island isolation regions.
In general, memory devices are faster and more compact than ever. However, there remains a demand for ever faster and/or more compact memory devices.
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a process for saliciding the word lines in a virtual ground array flash memory device without saliciding the substrate between word lines, which could cause shorting between bitlines. According to the invention, in a process for manufacturing virtual ground array flash memory devices, a salicide protect layer covers the substrate between word lines in the core region while the tops of the word lines are exposed. The salicide protect layer can be a spacer material, a dielectric material, or other material and can be formed solely to provide salicide protection, or as part of a routine step, such as providing spacers adjacent gates. The salicide protect layer can be brought into the desired configuration by one or more of masking the substrate between word lines during an etching process, removing salicide protection material in the core by polishing, and forming a comparatively thick layer of salicide protection material in the core whereby the tendency of the salicide protect layer to follow the contour of the underlying structures is reduced. With the substrate between word lines protected by the salicide protect layer, the word lines are salicided.
The process of the invention produces virtual ground array flash memory devices with salicided word lines, but without shorting between bit lines. Even where the word lines are broadly spaced to accommodate bit line contacts, the salicide protect layer covers the substrate, while the tops of the word lines are exposed. The salicide protect layer prevents the substrate between word lines from becoming salicided.